Reset Query

First of all I assume that all the resets will be synchronous resets (if any asynchronous reset is present it will be inherently independent of the clock).

Then you have to analyze what will happen in the transient which takes place soon after the reset signal. If any "out-of-sync" transient is acceptable in your system then you can use a single reset signal common for the two clock domains.

If, on the other side, also the data produced by your system during the post-reset transient period are essential and cannot be worng, then you should think about a dedicated reset logic. This logic shall be fed by both clock signals and shall produce a "reset_release" signal for the faster domain which has to be asserted when the reset for the slower domain has been active at least for a clock edge.