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Altera_Forum's avatar
Altera_Forum
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18 years ago

Reset process on a XIO1100 PHY

Hi all, With the XIO1100 documentation, I tried to initialize it with a dev card based on Cyclone II. Unfortunately, I see with my logic analyzer that the signal PHY_STATUS is never de-asserted...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

It's okay I resolved the problem. In fact I have to assert the /RESET before the XIO signals me its stable power and rxclk by de-asserting PHYSTATUS. The XIO data sheet is especially bad and unprecise.. No chronograms at all for the initialisation, etc...

but does someone know, once the XIO ready, when does the de-assertion of rx_elecidle? Or if it's because a special or wrong mode in the board that mine is never de-asserted (=no symbol lock) ?

Thank you and best regards.