reset input signal

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http://www.xilinx.com/support/documentation/white_papers/wp248.pdf

"Active-High control signals should be used wherever possible in the HDL code or instantiated components"

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Interesting. But this applies to Xilinx devices, and only to Virtex-5 and later ones.

All Altera FPGA families have a programmable inversion for each one of the control signals. And it seems this was true for Xilinx as well, until Virtex-4. For some reason Xilinx decided to remove the programmable inversion feature on later devices.