Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

reset input signal

Hi. I heard that the reset signal is better in active low. Is it true? If it is true may i know why? thanks
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

They do not make sense inside the FPGA though. I use then externally though. And anyway you have to synchronize any external signals so why not sync and invert ? That is what I do.