Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Reset for PLL

I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I'm getting a similar error on a Cyclone V: 

Warning: RST port on the PLL is not properly connected on instance MAIN_PLL:MAIN_PLL1|MAIN_PLL_0002:main_pll_inst|altera_pll:altera_pll_i|general.gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock.

I have the PLL set to "Auto Reset" to no avail. Tying the reset to the PLL locked inverted does not work. The PLL will just stay in reset forever. It worked in simulation, but not in the chip.

I guess the only option is to tie reset to '0' and live with the hopefully erroneous warning.