Removing signaltap causes logic to work

Note that SignalTap shouldn't be any different than adding other HDL that brings nodes to a RAM. It shouldn't affect your design.

That being said, if you add SignalTap and compile from scratch, that is like running another seed and hence a different place and route. So my guess is that you have a timing issue and SignalTap causes a different place-and-route that causes the problem. (By timing error, I mean a path that isn't being analyzed properly, as it is meeting timing.)

Luckily, the one that fails has signaltap in it. Make a copy of the design(just being careful to preserve failing design), then go to Assignments -> Partitions Window. Set the partitions in your design(most likely it's just the default Top) to post-fit. This will lock down the placement and routing. Then open SignalTap and change the probe points to get closer to where your failing. Compile.

This will keep your design locked down, and it should continue to fail, while SignalTap can get you to monitor where the failure is occuring. It will probably take multiple iterations of changing the probe points. Good luck.