Honored Contributor
Honored ContributorHi Jan:
First a question: Is the ethernet controlled through the FPGA, or do you have a cpu with Ethernet on the board? The main concern here, is I want to know where the image is store in after it comes off the ethernet. There are a few ways this can be accomplished: One is through a uart slave core in the fpga that talks to ALTREMOTE_UPDATE megafuncton in the FPGA to write, verify and boot a secondary image in the EPCS. We have done it that way with success, but we wrote our own custom uart interface, with slip streaming, and addressing scheme to make it work. This is the best way, if you only have a uart interface, and no direct micro or cpu on the board. The second way is to wire up the EPCS directly to both the CPU and FPGA, so the FPGA can boot from this in active serial mode, then the CPU can take control and access the EPCS directly. This is a little more risky, in that at boot up, you must insure the FPGA can read from the EPCS as it expects. We have done this when we had a small micro on the design that didn't have it's own external flash memory to store the bitfile. I don't really like this method however. A third way, if your CPU doesn't require the FPGA as part of it's boot process, is to have the CPU program the FPGA at each boot up in passive serial mode. This way the image is stored in the CPU's flash memory. We tend to use this most often if there is a master CPU in the design outside of the FPGA. I work for INFINETIX, an engineering consultant group. If you are working for a company with specific needs we can help you out. www.infinetix.com. If you are a student, working on a project, keep asking specific questions as you go along and get stuck, people on the forums are pretty good. Pete
