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Hello,
While debugging with the AS interface of the FPGA, I had found that the SPI sends the address as 24 bits even though the EPCQ used is 256.
For example, to know the behavior at FPGA configuration , I tried an address 0xABCDEF98 and confirmed with signal tap that the address is written correctly at the data_in port of the RSU module!
Surprisingly, the data in SPI bus is 0x0b, 0xAB, 0xCD, 0xEF 0x00 ... Seems the EPCQ 256 controller communicates 24 bit address, instead of 32 bit.
Does this mean that I forgot to use some options for the FPGA, to enable 4 byte address access of the EPCQ-256 ??
Thanks in advance for your advice.
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After analysing the wave forms of the SPI interface of EPCQ in the Application mode, I have found that the EPCQ device started sending the configuration image data to FPGA just after receiving 3 bytes of address, instead of 4 bytes of address. In both the application and factory mode, the dummy cycles were 4 clocks. It seems, there is a difference in the Address Configuration in the Application mode; the EPCQ controller is in 4 bytes mode whereas the EPCQ device is in 3 bytes.
To confirm this, I have tried a function call "epcs_enter_4_bytes_mode" (obtained from the epcs_commands.c provided in HAL) at NIOS side before the reconfig command, with the belief that it would enable "4 Byte Address Mode" corresponding to 4BYTEADDREN (defined in the Datasheet of EPCQ device). The result was positive. The FPGA at Application Mode configured well (the blinking LED @ Application comfirmed the config)
Can anyone guide for:
If 4BYTEADDREN mode is causing the issue, why doesn't it make a problem in configuration of FPGA after POR?
Is there any "Non Volalite Configuration register" (NVCR) to activate this mode premenantly?
How can I write "4 Byte Address Enable" in this NVCR? Is there any special NIOS2 command or JTAG operations available for this?
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