Honored Contributor
Honored ContributorHello,
The analysis of the wavefroms at SPI interface reveals that in the Application mode, the EPCQ device started sending the configuration image data to FPGA just after 3 bytes of address were received, instead of 4 bytes of address. In both the cases the dummy cycles were 4 clocks. I guess there is a difference in the Address Configuration in the Application mode; the EPCQ controller is in 4 bytes mode whereas the EPCQ device is in 3 bytes. To confirm this, I have tried a function call "epcs_enter_4_bytes_mode" (obtained from the epcs_commands.c provided in HAL) at NIOS side before the reconfig command, with the belief that it would enable "4 Byte Address Mode" corresponding to 4BYTEADDREN (defined in the Datasheet of EPCQ device). The result was positive. The FPGA at Application Mode configured well (the blinking LED @ Application comfirmed the config) Can anyone please tell me : If 4BYTEADDREN mode is causing the issue, why doesn't it make a problem in configuration of FPGA after POR? Is there any "Non Volalite Configuration register" (NVCR) to activate this mode premenantly? How can I write "4 Byte Address Enable" in this NVCR? Is there any special NIOS2 command or JTAG operations available? Please share us, if it exists. Has anyone modified the boot_loader_epcq256_bits_cv.s to obtain a customised boot loader?
