Honored Contributor
Honored ContributorThe real problems start when you need to use PCIe.
AS tends to be too slow to meet the PCIe reset timings, a 'double configuration' is almost bound to be too slow. CVP can be used (on some parts) to download most of the fpga image over PCIe, but it isn't at all clear to me that it is possible to build multiple images that can be loaded as alternatives - unless they are all built at the same time, or as a direct development sequence. In particular I can't imagine a support group being able to build a bug fix that can actually be loaded. This means that any (non-TAG) field upgrade will not only need the actual image for the fpga, but any failure will require JTAG to fix. With PS a jumper could be used to download a small (non CVP) factory image from a different part of the EPCS memory.
