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kd9's avatar
kd9
Icon for New Contributor rankNew Contributor
4 years ago
Solved

regarding config pins voltage levels

will we connect nstatus, nconfig, and config_done to 2.5V in cyclone 10LP in PS mode? These signals are going to processor/DSP(ADSP-BF534BBC-4A) that's working on 3.3v logic(attached the acceptance l...
  • FvM's avatar
    FvM
    4 years ago

    Hello,

    in case of doubt follow the Cyclone 10 LP Device Family Pin Connection Guidelines strictly.

    If using a 3.3V PS configuration host, I would prefer to power the respective VCCIO with 3.3V, but 2.5V should work as well. In any case, the warnings about maximal FPGA input voltage should be observed and measures against possible overshoot of externally driven signals taken, e.g. source series termination.

    There faults in your schematic snippet like 10k terminated MSEL2 pin.

    Unused CLK inputs are flagged as GND+ in the pin list, means, they should be connected to ground or another signal. See also pib connection guidelines.

    Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
4 years ago

Hello,

in case of doubt follow the Cyclone 10 LP Device Family Pin Connection Guidelines strictly.

If using a 3.3V PS configuration host, I would prefer to power the respective VCCIO with 3.3V, but 2.5V should work as well. In any case, the warnings about maximal FPGA input voltage should be observed and measures against possible overshoot of externally driven signals taken, e.g. source series termination.

There faults in your schematic snippet like 10k terminated MSEL2 pin.

Unused CLK inputs are flagged as GND+ in the pin list, means, they should be connected to ground or another signal. See also pib connection guidelines.

Frank