regarding block schematics

Hey guys im having some trouble working with block schematics.....What i intend to do is to connect several VHDL blocks via the block schematics...But i am some trouble as the name conflicts with top level entity.....Can u give me a detailed procedure to go about this programming...What i do is generate several VHDL files.....and latter start a new project and add these files.....but i am getting this error of the text design file should contain a logic section....this leaves me perplexed as I have written an entire VHDL code for it.....