Regarding an 8bit down counter

A counter can be implemented using a T flip-flops chain with the output (q) of previous clocking the next. This works, but has several clock skew problems related with the multiple clock domains introduced.

This is the reason that is preferred the solution using the adder and register.

lpm_counter simply uses mux and counter efficient versions by manipulating the logic cells (lcell) directly.

Check the RTL with RTL viewer.