Regarding an 8bit down counter

hi,

i dont agree with the argument that its ok to implement a counter with a mux, adder and a register. an adder is a data path element and it will induce more delay in my design. morever, an adder will unnecessarily consume more logic elements. To avoid this, i read somewhere to use the "lpm_counter" which will make my design incompatible with other vendors. Plz, can anyone suggest a way to work around this prob?

thanks in advance,

sumanth