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hi,
i designed an 8bit down counter by referring the "advanced synthesis cookbook". but the RTL viewer is showing a MUX, an adder and an 8bit register to represent this counter. is this correct? should i not expect a counter block instead? implementing an adder for a counter does not make sense to me. Let me know your thoughts regarding this.
thanks,
Sumanth
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hi Sumath,
how do you are the counter descript ? I assume you wrote something like this (Verilog)
counter <= counter + 1 , that's you Adder
Maybe you have defined a reset :
if (reset) counter <= 0;
else counter <= counter + 1 ; that's maybe the MUX
Adder and Mux is ok for a counter.
Honored Contributor
