Reference design (RapidIO) with errors ??

Hello,

I have found the following reference design for RapidIO.

https://www.altera.com/downloads/thank-you.html?swcode=www-ref-srio-6488

This reference can really help me because I was looking for a reference (for Linux actually, I don't know which OS fits for this refence , yet it can also help if it works).

It seems that (maybe) there are missing files for this reference:

I have found srio_main_full.c, but I can't find many symbols such as :

TX_DATA_BASE, RX_DATA_BASE, and many more...

I also find it strange to see that the DMA destination is 0 (?) according to these lines:

//dest_buffer = (int *)RAPIDIO_IO_WRITE_SLAVE_BASE;

dest_buffer = 0x00000000;

I have also found a pdf explaining the reference design:

https://www.altera.co.jp/content/dam/altera-www/global/ja_jp/pdfs/literature/an/an568.pdf

Yet, I still don't understand how the dma operations here are responsible for rapidIO transaction:

pkt_id = 0;

...

IOWR_32DIRECT(STATS_BASE, 0, 0x00000010); // turn off shadow transfer in stats module

IOWR_32DIRECT(DMA_WRITE_BASE, 24, 0x00010000); // bit 16 = soft_reset

IOWR_32DIRECT(DMA_WRITE_BASE, 24, 0x00000000); // bit 16 = soft_reset

IOWR_32DIRECT(DMA_READ_BASE, 24, 0x00010000); // bit 16 = soft_reset

IOWR_32DIRECT(DMA_READ_BASE, 24, 0x00000000); // bit 16 = soft_reset

... // limit targeted address space to 2**16-1

target_address = (pkt_id & 0x0000ffff) * (payload);

//printf("target address : %x \n", target_address);

// setup the DMA write operation

IOWR_32DIRECT(DMA_WRITE_BASE, 4, (int)tx_data);

IOWR_32DIRECT(DMA_WRITE_BASE, 8, (int)target_address);

IOWR_32DIRECT(DMA_WRITE_BASE, 12, payload); // page size length register in dma

// not needed since enable_soft_burst is zero

// IOWR_32DIRECT(DMA_WRITE_BASE, 16, payload/4); // stride in cycles

// bit 0 is the continuous mode operation

// bit 1 is enable_soft_burst

// bit 2 is

// bit 3 is the go bit

IOWR_32DIRECT(DMA_WRITE_BASE, 24, 0x8); // go_bit=1, enable_soft_burst=0, continous mode=0

// setup the DMA read operation

IOWR_32DIRECT(DMA_READ_BASE, 4, (int)target_address);

IOWR_32DIRECT(DMA_READ_BASE, 8, (int)RX_DATA_BASE);

IOWR_32DIRECT(DMA_READ_BASE, 12, payload);

// wait for write dma to complete

rdata = IORD_32DIRECT(DMA_WRITE_BASE, 0);

wr_dma_done = (0x00000001 & rdata) == 0x00000001;

//printf("waiting for write dma done \n");

while(!wr_dma_done){

rdata = IORD_32DIRECT(DMA_WRITE_BASE, 0);

wr_dma_done = (0x00000001 & rdata) == 0x00000001;

//printf("write dma base 0 %x \n", rdata);

}

//printf("write dma done \n");

// clear write done bit

IOWR_32DIRECT(DMA_WRITE_BASE, 0, 0x0);

Does anyone knows ?

Thank you,

Ran