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Altera_Forum
Honored Contributor
Honored ContributorRef Clock Pin 10G ATX PLL
Hi, In the Stratix IV Device Handbook Volume 2, page 1-197 they say: "For the 10G ATX PLL, Stratix IV GT devices only allow driving the reference clock source from one of the dedicated r...
Altera_ForumHonored Contributor
Honored ContributorSolution/Workarround:
Since the 10G ATX PLL can only drive 4 GXB channels (according to the Stratix IV GT Errata list), the CMU0 PLL of each GXB block is used to generate the clock and for this PLL there are dedicated REFCLK ports for each of these PLLs.
