Reduce clock frequency when system clock is dynamic

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Actually I am not sure what the min/max range of the dynamic clock is.

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Well, until you know that for certain using that dynamic clock for a reference, or anything else, is nigh impossible.

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If I can config the on-board clock to be fixed frequency I can of course do that, but I am not sure how. Do I need to create a Synopsis Design Constraint (SDC) file and then calculate the frequency or is there another way to obtain fixed frequency on the on-board clock?

Thanks.

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Well, any 'on board clock' (if present) should have its parameters listed in a user manual and/or schematic. It would usually be a fixed frequency crystal oscillator attached to a specific FPGA pin. You have to look at your board, read the user manual, or read the schematic (I assume you have access to the latter two items?)

You could then use that frequency to help define your SDC contraints for layout and timing analysis.

update: Itappears the 5m160ze64 part you are using has an internal oscillator in the UFM block with an output that can range from 3.9 to 5.3 MHz. The exact frequency is not programmable, it will vary from device to device, and over temperature and voltage. So it could conceivably be used as an (internal) reference, assuming you can live with the frequency variation.