Reduce clock frequency when system clock is dynamic

What is the min/max range of the dynamic clock? What is the rate of change of the dynamic clock?

The simple solution of course would be to just add a fixed 50MHz (or whatever) crystal oscillator part to provide a constant reference into your FPGA, and divide it down to 10Hz (or whatever).

Without having some sort of fixed reference it is impossible to know how much to divide a dynamic clock by to achieve a constant 10Hz output.

You seem to be looking for a very complex solution to a problem that is much easier to solve using a more standard approach (a fixed frequency source).