Forum Discussion
Altera_Forum
Honored Contributor
9 years agoOff the top of my head I can't think of any way to do this purely in software.
One approach would be to include a one-shot monostable circuit between an FPGA IO pin and the nCONFIG line. (e.g. http://www.linear.com/product/ltc6993-1) When the FPGA drives a signal out to the monostable, then the monostable will output a nice controlled-width pulse to the nCONFIG pin. Without a monostable, the FPGA would cut its own throat as soon as it drove the nCONFIG line and so the reset pulse width would just be a glitch and unreliable. The other way to do it is to have a watchdog chip driving the nCONFIG line. I use these on all my FPGA boards. (e.g. MAX6369KA+T) Your application would normally kick the watchdog at regular intervals (I do this from the software on my NIOS-II embedded soft-processor). To re-configure your chip, just let the watchdog time-out.