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The output of the pll are mixed, i-e if clk0 should become 24MHz and the 4 others 85MHz, after reconfiguration I have 4 clocks at 85MHz but the 24MHz one is clk 1... or clk3... or clk4... It changes at each compilation.
Sometimes I only get clocks at 85MHz but it doesn't happen often.
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I have seen very similar results in one of my designs before. It seems when the fitter is optimizing, it sometimes chooses different PLL outputs than you actually specified in your design. If you check the PLL usage section in the fitter report, you can see how the outputs are mapped. I found I had to tweak my PLL reconfig data accordingly. Unfortunately, the mapping can change on subsequent compiles without warning messing it all up again. I never found a good way to deal with the problem. If you find a good work around or anyone else knows one, I would like to hear it.
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