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Honored Contributor
Honored Contributorreconfig PLL in CycloneIII
hi everybody, I'm using an EP3C10 and I have to reconfigure one pll. I've tried with the altpll_reconfig but i can't be able to use it properly. Then I have made my own VHDL block to gener...
Altera_ForumHonored Contributor
Honored ContributorHi,
I have an other problem with the pll reconfiguration. My FPGA is an EP3C16 and has 2 pll. Until now, I only reconfigure one pll but now, I'd like to reconfigure both. I have done the same thing to reconfigure the second pll but it doesn't go well. The output of the pll are mixed, i-e if clk0 should become 24MHz and the 4 others 85MHz, after reconfiguration I have 4 clocks at 85MHz but the 24MHz one is clk 1... or clk3... or clk4... It changes at each compilation. Sometimes I only get clocks at 85MHz but it doesn't happen often. I tried several way to perform the configuration : with one pll_reconf and several rom and with several pll_reconf but it doesn't change anything. has anyone an idea to solve my problem? thanks!
