It's easiest to get your feet wet on PLL reconfiguration by using a MIF. Let Quartus II generate a MIF with your initial PLL settings. Then, open that MIF in a text editor. Don't open it in Quartus II, it only shows a matrix of numbers. If you open it in a text editor, you'll see all of the comments for where the parameters are at. Makes it easy to make adjustments. Change the counters on the C0 output and save the MIF. Compile your design, use the altpll_reconfig block with that MIF defined, pulse the reconfig port, and then see if the output clock changed according to your new factors you wrote to the MIF.
The altpll_reconfig takes care of all the timing and handshaking signals, it's tough to use the figures in the handbook since they are usually functional diagrams and not necessarily timing information. Perform timing simulation to get the real timing parameters.