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I'm not sure of a good way to compare the two design types. You could probably estimate the gate count for an ASIC which would be similar to how I count the LE usage for small blocks of hardware in an FPGA.
In an ASIC I would expect the XOR gate to be larger and slower due to the additional transistors required when compared to an AND gate. Oddly enough I have never implemented an ASIC so I might be oversimplifying things. Just like with FPGAs the sythesis tools may change the footprint to optimize for speed, area, and power.
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Thanks very much! Now I understand much better =)
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