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Honored Contributor
Honored ContributorReal Implementation
Hi, Say I have two architectures, A and B with A having complexity of 36 ANDs, 99 XORs. Meanwhile B having complexity of 37 ANDs, 105 XORs. The complexity here is derived directly from its arit...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Is it a real problem? Do you mean AND and XOR with only two inputs each? Depending on the actual logic expression, they are combined by Quartus to a smaller amount of either four- or six-input LUTs (depending on the FPGA family). So the required number of LEs can be different. You didn't talk about registers at all. --- Quote End --- The input is just a one byte std_logic_vector and the architecture performs several simple arithmetic using only AND gates and XOR gates.
