Real Implementation

On a Cyclone device for example (4 input LUT) you could have something like this consume a single logic element:

assign x = a & b;

assign y = c & d;

assign z = x & y;

The reason why is in the end z is just a & b & c & d which fits into a 4 input lookup table. FPGAs treat the inputs a-d as the address of the lookup table in the logic element. When you program the FPGA the table has all 16 addresses programmed with the various combinations of a-d. So in the example above addresses 0-14 would be '0' and address 15 would store a '1'. Then when a-d are all high they hit address 15 and a '1' comes out of a LUT.

Like FvM said the results can vary depending on the lookup table size and the logic function you attempt to implement (and what synthesis decides works best). The Stratix II and beyond line of FPGAs include ALUTs which can be split into two lookup tables of various sizes with two registers as well. The logic footprint of FPGAs doesn't directly map to what you would expect from an ASIC since the logic functions are implemented in memory and not gates.

Page 3 of this document gives you a pretty good idea what an logic element looks like: http://www.altera.com/literature/lit-cyc2.jsp