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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

The DC_FIFO issue of Cyclone 10 GX devices

Hello Guys, We are using 10CX220F780 and 10CX105F780 devices now. They are communicating thru XCVR. So one DC_FIFO is realized between RX received data and user logic fabric.   This DC FIFO operat...
Core Logic
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hi,

May I know which Quartus version is being used? Please share a smaller version of your design to replicate the issue on our side. Simulatable design is preferred.

Parallely on your side, I would like to see the DC_FIFO ports in the signal tap. Please add as many signals at the FIFO level, including 'aclr' to the signal tap and send us a screen shot. Additionally add XCVR rx_ready signal as well.

 

I didn't quite understood what you mean by "we don't open 'aclr' port". Do you mean you never assert and de-assert the 'aclr' port? Please clarify.

 

Regards,

Altera Tech Support

Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Also, let us know all the FIFO IP settings that you have used.

 

Regards,

Altera Tech Support

  • MinzhiWang's avatar
    MinzhiWang
    Icon for Occasional Contributor rankOccasional Contributor
    1 month ago

    Hi Ash,

    Sorry for the delay of reply. Our FIFO parameters are all used default settings, except the ones of above block symbol indicating. They are 32-bit data width, and checking read-side and write-side ports of empty/full/usedw.

     

    BTW, I tried your suggestion of checking aclr port, now the block symbol as following image. Then DCFIFO will work well by applying asynchronized clear control. But I don't know why this is necessary for it?

    Best Regard