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Ad13
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4 years ago

JTAG - CLK Pin limited to 0.7V

I have 2 x custom boards with 10CX085YU484E6G and a MT25QU01GB flash device that have been working fine. However, for some reason Quartus changed the device and when I last programmed the FPGA and F...
Ad13's avatar
Ad13
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4 years ago

Hello Aiman,

Thanks for your response.

I have verified multiple times the pull-up and pull-down resistors on the JTAG lines.

The TCK signal is clean, crisp and not in any way noisy - but just clipped at 0.7Volts. TCK is pulled low through a 1K resistor.

I've tested with 4 cables - a mix of Altera USB Blaster 2, 1 and 3rd party tools. The actual level of the TCK signal changes depending on the cable used, with USB Blaster 2 being the best.

Pin 4 is at 1.8V, which is the VCCIO level and VCCPGM level.

All rails are as expected - the device exits reset as it is configured for active serial (via MSEL) and I can see it try and load an image from the flash device.

As a test I added a 10K pull up resistor to TCK with no download cable attached, and similarly it only goes to 0.7V.

Must be a damaged input? How can I have done this by programming with the wrong image? It really was immediate, on 2 boards, after programming with the wrong device selected. Could it have sent one of the reserved JTAG codes?

Many thanks,

Adrian