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songsong96's avatar
songsong96
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3 years ago

How do I select an FPGA chip with a high-speed system clock available?

Our team wants to implement an FPGA system that controls DAC Resolution 1ns width. The FPGA now in use is using Cyclone V (5ceba2f23c7). The 40MHz crystal clock is received from the outside, multipl...
FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi songsong96,

this thread has been marked as inactive and will be transitioned to community support because there is no update received from you in a while.

If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread.

If you feel your support experience was less than a 9 or 10, please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

Thank You.

Regards,

Fakhrul


songsong96's avatar
songsong96
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3 years ago

Hi Fakhrul

1. Is The fastest clock that can be made with ALTPLL is 40 pages of -c7 grade refers to the peripheral clock (155Mhz(b))? We receive a 40MHz clock from the outside and put it in ALTPLL INPUT. If I can use the clock of PLL OUT to 550 MHz(a), what am I missing?

What is The max of the fastest clock that I think can be made with ALTPLL is one of a, b, a, b, c, d, e?

2. I learned about ALTLVDS by looking carefully at the datasheet 46 page you showed me.
We asked because we wanted to control dac over 500 Msps. Can I control the 16-bit data bus at a high speed if I use ALTLVDS before that? According to DATASHEET, it was able to produce an OUTPUT of 400 MHz.
I'm looking for CYCLONE's LVDS EXAMPLE.


https://www.intel.com/content/www/us/en/docs/programmable/683520/22-1-20-0-1/design-examples.html
I found the link above, but I couldn't find the EXAMPLE FILE. I'm just downloading the PDF file and studying it.

Thanks to you, I'm learning a lot for you.


Regards,

Songsong96