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mriemleit's avatar
mriemleit
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4 years ago

DDIO Output Timing Errors on a Source Synchronous Interface (RGMII)

Hi Intel Community, I've got problems with the timing of a RGMII Interface. In my design the FPGA imitates an Ethernet PHY. So the FPGA has to delay the RX and TX clock by 90 degree internally....
pnp's avatar
pnp
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4 years ago

Edit: Sorry, I should have read more thoroughly--you're referencing timing violations, not a broken interface.

Best regards,

Paul

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Hi,

I'm not sure if this relates to your issue, but I got recently got burned trying to apply that Application Note by the DDIO IP's port naming. It turned out my forwarded clock was inadvertently flipped 180 degrees, breaking my source synchronous interface:

https://community.intel.com/t5/FPGA-Intellectual-Property/GPIO-DDRIO-IP-output-swapped-datainhi-datainlo-inverts-forwarded/m-p/1317982#M24752

The documentation for that IP is not my favorite.