Occasional Contributor
Super ContributorI not sure about the lpm_counter structure as I don't have the visibility but a simple binary counter is just an adder with one input tied to 1 followed by a register. Our Quartus tool has the counter verilog design template in which you can just pop it into your project and use it right away.
In the new Verilog .v file, right-click to opens the context menu, scroll to Insert Template, a window Insert Template will pop up, choose Verilog HDL > Full Designs > Counters > Binary Counter.
You mentioned that the Verilog version fails, could you help to clarify what type of failure do you refer to? Have you try to test it at 400MHz input clock in which the first version passed?
Occasional ContributorHi,
I used the LPM_COUNTER out of the IP catalog I get together with Quartus Premium lite. Here I can't look into with the TCL viewer tool. This IP works fine at 400MHz.
But I need some arithmetic, so I started with Verilog. It is also easier to change the design editing some lines of code than drawing boxes and lines (block design).
Now it fails with 400MHz and I have to go down to 100Mhz.
After verification of the design, I split it into a counter/comparer part and an arithmetic part. Arithmetic is still Verilog, but for the counter and comparer I use the LPM_XXX IP blocks out of the library.
Now it works at 400MHz again.
I want to ask the community before I started this amount of work, to draw the schematic. It also could be, that it isn't faster than the Verilog design.
But now I can say and I know, that a simple counter, which is an adder and a register after the Verilog compiler is slower than the LPM_COUNTER library block.
And if you take a look at the old logic chips (74xxx) you will see, that a binary counter didn't use an adder to simply increment by one each clock cycle ...
With best regards
Gerhard
