Random results on FPGA

Hello,

I'm using altera devices for about 10 years with quartus or quartus + synplify pro.

I'm currently struggling for about a month !!! on this issue:

Using the same netlist from synplify pro, the same timing constraints, and doing the place and route with quartus,

I can get total different results on FPGA (stratix III): fully working, or failing on first HW accesses.

The IP in the FPGA uses a lot of clock gating and I think that Quartus is not doing a good timing analysis (timequest reports no timing violations and the design is fully constrained),

leading to such random results.

Did you ever face such problem at your place ?

Metastability report in timequest reports no problem.

Resets are ok.

Cooling the FPGA does not change anything.

I never faced such situation before.

I need help !

Alex