Ram Allocation

Like pancake said if you disable signaltap those memories shouldn't be used in your design. Depending on the IP core and how your synthesis settings are setup there could be some tradeoffs between LEs and on-chip memories or RAM consolidation that can occur. Before diving too deep I recommend taking a look at the memory block usage for your entire design and determining if there is anything you can do to conserve memory resources. The memory usage is shown on a hierarchical basis so you should be able to figure out what HDL/IP is using up the blocks. You can find this in the fitter report or by adding extra columns to the project navigator when you are inspecting the hierarchy of your design.