Honored ContributorHello,
How does one modify the RAM within a design. I am trying to get my design to fit on a Cyclone III 40 instead of a 55 by deleting all the signal tap files on it to fit. In the process I discovered that the signal tap files are using too much ram and while I can delete them I need to get rid of the RAM they use as well to make the design fit on the smaller 40 chip. Any suggestions? Thank you
Honored Contributorif you disable SignalTap in Assignments > Settings > SignalTap II it shouldn't use any RAM associated with the STII instance
Honored Contributorit depends on "sample depth" and number of "node" signals.
the bigger information you require the bigger memory you consume.Honored ContributorLike pancake said if you disable signaltap those memories shouldn't be used in your design. Depending on the IP core and how your synthesis settings are setup there could be some tradeoffs between LEs and on-chip memories or RAM consolidation that can occur. Before diving too deep I recommend taking a look at the memory block usage for your entire design and determining if there is anything you can do to conserve memory resources. The memory usage is shown on a hierarchical basis so you should be able to figure out what HDL/IP is using up the blocks. You can find this in the fitter report or by adding extra columns to the project navigator when you are inspecting the hierarchy of your design.
