I'm building a Binary Game for my final project in Digital Logic and Design and a small portion of this game I'm building uses a countdown timer to show how much time you have left in your round. I hooked up a clock to my output and got it running, counting down 1 second at a time. Then I hooked up a second clock (same clock but I changed the clock divider by a factor of 10) to my other output and was wanting to have it countdown in 10 second intervals. And it does countdown in 10 second intervals the issue is that it counts down at the wrong time. The 10 second countdown is triggered on the 5 sec of the 1 sec. clock countdown. So I get 99.98.98.97.96.85.84.83.82.81.80.89.88.87.86.75.74.73.72.71.70.79....and so on..... Any quick fixes? Or has anyone had this issue before? I'm a complete newbie so talk slow and use small words :-P

you need to align the two countings such that when counter1sec = 0 ~ 9 it aligns with counter10sec 0 for 10 clocks. If you are using two independent clocks you are likely to run into trouble. use fast clock as usual for both counters then use clockenable e.g. when counter1sec = 9 then count down the other counter.

Just using 1 clock going into 2 different clock dividers with different values

In that case all you need is to make sure your divided clocks are in phase. But to avoid the hassle I will run counter1sec on its clock starting from say 1000 at reset release. Then I will run counter10sec starting from say 100 after reset release on same clock but use the other 1/10 clock as clockenable to count down. Thus at start after reset release it should align like this: 1000 999 998 997 996 995 994 993 992 991 990 ... 100 100 100 100 100 100 100 100 100 100 99 ... and don't forget to keep clock enable under reset till release.

This is the clock divider that I'm using the only difference between my 2 clock dividers is the "integer :=25000000" in one and "integer :=250000" in the other...what exactly do I need to change to have them lined up? Thanks in advance for any help... LIBRARY ieee; USE ieee.std_logic_1164.all; ---------------------------------- ENTITY clk_div is generic(DIVISOR : integer := 25000000); port( clk: in std_logic; x: out std_logic ); END clk_div; ----------------------------------- ARCHITECTURE freq OF clk_div IS signal temp: std_logic := '0'; begin process(clk) variable counter: integer range 1 to DIVISOR; begin if(clk'event AND clk = '1') then if(counter = DIVISOR) then counter := 1; temp <= NOT temp; else counter := counter + 1; end if; end if; end process; x <= temp; END freq; -----------------------------------

The problem you have may be creating "ripple clocks". These are bad. A ripple clock is where you use registers in your design to act as a new clock. What you should be creating instead are clock enables. To create a clock enable structure try: PROCESS(reset, clock) BEGIN IF (reset = '1') THEN counter <= 0; clock_enable <= '0'; ELSIF (rising_edge(clock)) THEN IF (counter = counter_limit - 1) THEN clock_enable <= '1'; counter <= 0; ELSE clock_enable <= '0'; counter <= counter + 1; END IF; END IF; END PROCESS; Aside from that, your code to generate the count down behavior should probably make use of a good synchronous reset. Building a process with an asynchronous reset and a clock enable looks like this: PROCESS(reset, clock) BEGIN IF (reset = '1') THEN --put initial conditions here ELSIF (rising_edge(clock)) THEN IF (clock_enable = '1') THEN --put code here END IF; END IF; END PROCESS;

Quirk with my clocks | Altera Community

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Altera_Forum
Honored Contributor
13 years ago
I just wanted to give a big thank you to everyone who attempted to help me with my project...I've finally gotten to a point where I could turn it in right now if I had to which is a pretty awesome feeling since I still have a week and a half to work on it.

The only functionality that I have not yet been able to meet that I had set out for myself is retaining a high score for my game, and then displaying that score on the LCD screen.

My thought is that I could use the lpm_compare megafunction to determine if the new number is higher than the old number and then output the higher of the 2 but it doesn't seem to work, the lpm_compare works just not when I make my circuit dynamic and have changing values.

Does anybody have any ideas or things that I should check out that might point me in the right direction? We haven't covered any sort of rom or ram in our class...I tried figuring out the different memory megafunctions but I'm struggling.

I appreciate any help...
Altera_Forum
Honored Contributor
13 years ago
If I understood your requirement, you want to get maximum of a stream of values. Then you can use a register with a bit of logic(assuming your stream is reg1 with positive values only):

process(reset,clk) begin if reset = '1' then reg2 <= (others => '0'); elsif rising_edge(clk) then if reg1 > reg2 then reg2 <= reg1; end if; end if; end process;

Good luck with your scores
Altera_Forum
Honored Contributor
13 years ago
Thanks Kaz, I got my high score working now, I didn't end up using the code you wrote but it got me thinking in the right way and I was able to build what I needed in the block diagram because of it.

Last question, I swear...as of right now I've got a 8 bit wire just dangling out there in my schematic and I need to convert it's output to display on the LCD display on the DE2 board. Ideally I'd like for the display to read

"The Binary Game
High Score: XX"

Where the 2 Xs are the 2 digit high score...I've been reading on this site but I have absoluetly no coding experience and haven't a clue where to even begin or what I would even need to write to get it to display that way. We didn't use the LCD at all in my labs and was just something I wanted to see if I could get to work to make my project just a little something extra.

When I get this thing working I'll throw a video on youtube and post the link here.

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Quirk with my clocks

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