Questions regarding interfacing of & accessing custom hardware blocks

Hi again,

Ok, the VHDL code has been completed, and decided to use the proposed form of interfacing with avalon as above, but some modifications, since i want to write to multiple input signals:

 begin
process (clk)
begin
 if clk'event and clk = '1' then
  if reset_n = '0' then
   readdata <= (others => '0');
   else
   if chipselect = '1' then -- our BCC is selected
   
    if read = '1' then   -- if the hardware wants to write to avalon (avalon should read from hardware)
     if flag_bc = '1' then -- if a branch_cost is done
     readdata <= "11111111111111111111111111111111";
     readdata <= result;
      
     elsif flag_bc = '0' then -- if branch cost is not done, just send 32 zeros
     readdata <= "00000000000000000000000000000000";
     end if;
    end if;
     
    elsif write = '1' then -- if write is asserted (avalon should write to the hardware)
     
     case count is  -- The order in which inputs are fed from C is fixed
      when "000" =>
      sys_rec <= writedata;
      count <= "001";
      when "001" =>
      sys_ref <= writedata;
      count <= "010";
      when "010" =>
      par1rec <= writedata;
      count <= "011";
      when "011" =>
      par1ref <= writedata;
      count <= "100";
      when "100" =>
      par2rec <= writedata;
      count <= "101";        
      when "101" =>
      par2ref <= writedata;
      count <= "110";        
      when "110" =>
      x <= writedata;
      count <= "000";        
     end case;    
   end if;
  end if;
 end if;
end process;

With the following signals in the port declaration in the entity:

  signal clk, 
  reset_n,
  read,
  write,
  chipselect : in std_logic;
  signal readdata : out std_logic_vector(31 downto 0);
  signal writedata : in std_logic_vector(31 downto 0)
);

It seems to import in SOPC builder, with a warning:

avalon_slave_0: signal readdata appears 8 times (only once is allowed).

Also, the case conditional statement has been made so that i write from the C program, in a specific order, i.e. when it has received the first 32 bits, it assigns them to sys_rec, the next 32 bits are assigned to sys_ref and so on.

flag_bc is a flag which is set in another process as soon as result is computed.

When the flag is 0 i want the hardware accelerator to return 32 bits of zeros. When the flag is 1 i want it to send 32 bits of ones (to indicate that there is a result) and then afterwards give me the (32 bit) result.

Would this actually work as it is supposed?

I suppose i am reading from the register writedata, and sending to the register readdata. How do i know in which order they come? For example would readdata be at IORD(0x01001000,0) or would it be IORD(0x01001000,1) or something else...

If the rest of the vhdl can help anything, i can post that also, but it needs to be shined up a bit.