Honored Contributor
Honored Contributoraustin944, I think we are talking about two different things here. I see on page 28 of the datasheet where it says to set 06h for the write enable operation; however, I'm using the Altera ASMI parallel core to interface to the epcq which gives me the write enable operation as a signal that I just need to assert as 1 in order to enable a write operation. I'm talking about setting the status register bits for sector protection and a description can be found on page 18 of the datasheet for epcq. This is where I am trying to use the block protection bits in the status register in order to protect and unprotect sectors of the epcq and this is where I am running into issues. the ASMI parallel core datasheet says
--- Quote Start --- The IP core uses only bits 2 to 3, or 2 to 4 for EPCS devices, and 2 to 5, or 2 to 6 for EPCQ/EPCQL devices out of the 8 bits for block protection. The rest of the bits have other meanings for the ASMI operation, and cannot be overwritten by the sector protect operation. --- Quote End --- So I am dealing only with bits 2 through 6 of the status register for sector protection. What I was truly trying to do is protect sector 0 and unprotect everything else which on page 23 of the EPCQ datasheet shows that as BP0 = 1 and TB = 1 and that maps as bits 2 and 5 of the status register according to page 18 of the datasheet. So I set the status register bits as 00100100b (MSB->LSB) yet when I read the status register I see 00000100b (MSB->LSB) so I'm confused as to what happened to bit 5 as this also changes what sector is being protected. a_x_h_75, so then it seems it is concern that my data can be overwritten if the .jic file is large enough to fill up those sectors containing my data?
