Questions on PCIE communication protocol implementation in RIFFA

I am using Riffa PCIE coding in Altera DE4

1) According to the completion TLP in http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1 , why https://github.com/kastnerrg/riffa/blob/master/fpga/riffa_hdl/recv_credit_flow_ctrl.v#l65-l68 allocated 12 bits and 8 bits for data and header respectively ?

https://xlnx.i.lithium.com/t5/image/serverpage/image-id/39330i545994E23634BCA4/image-size/original?v=1.0&px=-1

2) For http://riffa.ucsd.edu/node/3 , why " Note that data on chnl_rx_data may begin to arrive before chnl_rx_ack is pulsed, but the fifo will never overflow. " ?

3) Why https://github.com/kastnerrg/riffa/blob/master/fpga/riffa_hdl/tx_port_channel_gate_32.v#l109-l124 and https://github.com/kastnerrg/riffa/blob/master/fpga/riffa_hdl/rx_port_32.v#l247-l286 using different number and types of FIFO ?