Questions about Rapidio II ip core

Hello!
I am trying to establish SRIO communication between Stratix 10 FPGA and Ti DSP. On the FPGA side, I used RapidIO II ip core in quartus 20.1. Now I found that the connection between them was failed.
Below are my questions:

Q1:
After powering on, does the FPGA and DSP automatically connect through SRIO? How do I know if the connection between FPGA and DSP is successful? Or What actions do I need to perform to make their connection successful?

Q2:
Is there an example design of S10 FPGA communicating with Ti DSP through SRIO?

Q3:
After powering on, In the RapidIO II ip core, signal port_initialized and link_initialized are always '0'. How to locate the problems? Is that a hardware connection problem?

Regards