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Hi.
I have a few questions about designing a ASIC that i hope some of you can shed some light on.
I currently use a 32bit ARM M3-Cortex MCU connected to a GSM-modem. I am planning to add Bluetooth and WiFi also. Lets say i wanted all this and maybe a DMA some RAM and a few ADCs in an ASIC. Pretty basic.
1. Can i get the HDL code for these components and easily add them together in an ASIC?
2. Are most of these components available in HDL for a royalty fee?
3. Is there a lot of ready made IP-Cores ready for implementation with the SOPC-builder for specifically this kind of thing?
4. Lets say the above mentioned components where to be integrated in one ASIC. What kind of size would a chip like that typically be? Using 90nm? 40nm?
5. Lets say I do the prototyping on one of the Stratix FPGA boards. What would it typically cost to make the first ASIC from a functional prototype on the FPGA board?
6. What kind of time window are we talking about from delivering the FPGA prototype to Altera until the first ASICs are available?
7. What price per chip are we talking about when mass production starts, not considering the initiation cost.
8. Any Links to examples resources and other things?
9. Any helpful hints/tips anyone?
Thanks!
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Hi,
are you talking about the Hardcopy Family offered by Altera or are you talking about a
"real" ASIC ? If your design requires certain analog stuff ( e.g ADC's) I'm pretty sure
that you can't get the ASIC from Altera. Have look to the Hardcopy Devices on the Altera
Homepage.
Kind regards
GPK
Honored Contributor
