Question on input delay

Hi,

whenever you have a synchronous input, you should apply timing constraints to it. A synchronous input is one where the input signal that goes into the FPGA pin is launched using the same clock that the FPGA uses internally to launch that signal. (in contrast to that, an asynchronous input is one where you apply two synchronization registers to avoid metastability).

And why? Well, let's assume the worst case: the signal is synchronous to the clock that the FPGA uses to launch it, but due to propagation delays, the signal happens to toggle exactly at the moment when the FPGA launches it (i.e. when a register inside the FPGA receives a rising clock edge). The setup- and hold-times of the register will be violated, which leads to metastability (see here (http://www.asic-world.com/tidbits/metastablity.html)), which in turn can cause synchronous logic to fail.

By applying an input_delay timing constraint, you're telling the FPGA design tool (Quartus) the characteristics of that input signal. When you run the static timing analysis tool (TimeQuest), it'll tell you whether the signal you're feeding into the FPGA is prone to such failure or not. If it is you can take countermeasures, e.g. changing the clock polarity (effectively shifting it by 180 degrees). The place&route tool can also do minor adjustments to the design to try to fix the timing (I'm not sure whether this applies to input pins, but output pins typically have a programmable delay for this purpose).

So if you just want to hack something together, and it happens to work, fine. But if you want to be sure that your design works long-term, over all specified temperatures and power supply voltages, and also among a series production, you better constrain your designs, so that you're warned early if you might run into timing issues.

Btw., here's a nice article about SDRAM timing: http://retroramblings.net/?p=515 (http://retroramblings.net/?p=515).

Best regards,

GooGooCluster