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均符's avatar
均符
Icon for New Contributor rankNew Contributor
5 years ago

Question for DDIO_IN IP

We wanna use DDIO_IN IP for capture data at twice the rate of the clock with a high-speed interface application in which the data is clocked at both edges of the clock. The freq. of clock from our f...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

Welcome to Intel Community.

Yes, you are right. Cyclone devices support DDR SDRAM and FCRAM interfaces at up to 133 MHz through dedicated circuitry. There are few guidelines for user to meet 133 MHz performance for DDR SDRAM and FCRAM interfaces as below:

  • The DQS signal must be in the middle of the DQ group it clocks
  • Resynchronize the incoming data to the logic array clock using successive LE registers or FIFO buffers
  • LE registers must be placed in the LAB adjacent to the DQ I/O pin column it is fed by.

For more details, you may refer to this Cyclone FPGA Family Data Sheet under section "External RAM Interfacing"--> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_cyc.pdf

Hope this helps.

Thanks

Regards,

Aida