Question about Monitor

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What exactly does a PCIe IP inside a FPGA do?

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If you do not understand PCIe at this level, then you need to listen to the Altera webinar's before attempting to simulate a system containing them.

PCIe is a specification that involves an electrical interface (the high-speed SERDES lanes), and a configuration/programming interface (borrowed from the PCI specification).

The FPGA IP core implements the physical interface using its SERDES channels, and Altera has implemented the configuration interface. Your designs can add custom functions to the BAR regions. The root complex version of the IP core needs to 'setup' the PCIe bus. The BIOS or Bootloader running on the device with the root complex would go out and 'enumerate' the PCIe bus, i.e., find all the devices and give them base addresses in the memory map of the root complex. The FPGA IP configured as end-points respond to the root complex with details about what they require in terms of resources on the PCIe bus.

If you do not understand the details of this, then you will not be able to get your simulation working, since your testbench code has to perform the functions of the BIOS/Bootloader to configure the PCIe bus before you can issue transactions.

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The signals from the PCIe bus enter the PCIe IP inside FPGA and then the signals enter the avalon fabric and then the RAM right?

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According to the webinar link I posted you, the PCIe IP can implement an Avalon-ST interface where you see transaction packets, and you have to write code for it, or it can implement a simple Avalon-MM master. In your case, it sounds like you are using the IP configured as an Avalon-MM master, which in turn connects to the RAM.

What is happening at the system level is you issue a high-level command from your fake host system, eg. a read, which in C code could be the dereferencing of a pointer, that read targets the PCIe root complex, which converts it into a PCIe packet destined for your end-point. The end-point captures the PCIe packet, converts it back into a read command, issues that read as an Avalon-MM master, and captures the read data. The PCIe core in the end-point then converts the read data into a PCIe packet, sends it back to the root-complex, the root-complex converts it back to a data value to return as read data. Its all very complicated :) Its even trickier if you look at a Qsys system, given that the transactions between masters and slaves are also converted into packets, but this time Qsys packets.

Cheers,

Dave