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Altera_Forum's avatar
Altera_Forum
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13 years ago

question about IO delay

external chip provid a clock signal to fpga, and I triger data output to fpga pins using this clock, but I found the delay between clock and data at fpga pins almost 10ns,then I can not let this clock align at center of data.How can I fix this problem?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    By defining proper timing parameters and doing correct PCB routing?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    There are two things contributing to those 10 ns; and two actions you need to take.

    First, there's a considerable delay from the clock input pin to the flip-flop's register pin, due to the clock distribution tree.

    This can be compensated by using a PLL in normal compensation mode: feed the input clock to the PLL and use the PLL's output clock to drive the logic.

    Second, there's also a considerable from the internal registers' output and the output pin.

    This can be greatly reduced by using the Fast Output Registers which sit in the IOB itself.

    You can get Quartus to use them by setting proper output delay constrains or by using the assignment editor.