question about buffer model in CPLD

Hi to all,

I'm trying to run this buffer code on CPLD with 128 MicroCells, which recieves 8-byte data continueslly and outputs the data between 50 ouputs.

I recieve the following error when trying to run the simulation:

"Error: Can't fit 312 registers in device"

Can I reduce the numbers of registers in my code?

// Buffer model

module Buffer_model (Data_In, WE,

D00_Out, D01_Out, D02_Out, D03_Out, D04_Out, D05_Out, D06_Out, D07_Out, D08_Out, D09_Out,

D10_Out, D11_Out, D12_Out, D13_Out, D14_Out, D15_Out, D16_Out, D17_Out, D18_Out, D19_Out,

D20_Out, D21_Out, D22_Out, D23_Out, D24_Out, D25_Out, D26_Out, D27_Out, D28_Out, D29_Out,

D30_Out, D31_Out, D32_Out, D33_Out, D34_Out, D35_Out, D36_Out, D37_Out, D38_Out, D39_Out,

D40_Out, D41_Out, D42_Out, D43_Out, D44_Out, D45_Out, D46_Out, D47_Out, D48_Out, D49_Out);

input [7:0] Data_In;

input WE;

output [3:0] D00_Out, D01_Out, D02_Out, D03_Out, D04_Out, D05_Out, D06_Out, D07_Out, D08_Out, D09_Out,

D10_Out, D11_Out, D12_Out, D13_Out, D14_Out, D15_Out, D16_Out, D17_Out, D18_Out, D19_Out,

D20_Out, D21_Out, D22_Out, D23_Out, D24_Out, D25_Out, D26_Out, D27_Out, D28_Out, D29_Out,

D30_Out, D31_Out, D32_Out, D33_Out, D34_Out, D35_Out, D36_Out, D37_Out, D38_Out, D39_Out,

D40_Out, D41_Out, D42_Out, D43_Out, D44_Out, D45_Out, D46_Out, D47_Out, D48_Out, D49_Out;

reg [3:0] Mem [0:49];

integer i;

initial

begin

for (i = 0; i < 50; i = i+1)

begin

Mem = 4'b0000;

end

i=50;

end

assign d00_out = mem[00];

assign d01_out = mem[01];

assign d02_out = mem[02];

assign d03_out = mem[03];

assign d04_out = mem[04];

assign d05_out = mem[05];

assign d06_out = mem[06];

assign d07_out = mem[07];

assign d08_out = mem[08];

assign d09_out = mem[09];

assign d10_out = mem[10];

assign d11_out = mem[11];

assign d12_out = mem[12];

assign d13_out = mem[13];

assign d14_out = mem[14];

assign d15_out = mem[15];

assign d16_out = mem[16];

assign d17_out = mem[17];

assign d18_out = mem[18];

assign d19_out = mem[19];

assign d20_out = mem[20];

assign d21_out = mem[21];

assign d22_out = mem[22];

assign d23_out = mem[23];

assign d24_out = mem[24];

assign d25_out = mem[25];

assign d26_out = mem[26];

assign d27_out = mem[27];

assign d28_out = mem[28];

assign d29_out = mem[29];

assign d30_out = mem[30];

assign d31_out = mem[31];

assign d32_out = mem[32];

assign d33_out = mem[33];

assign d34_out = mem[34];

assign d35_out = mem[35];

assign d36_out = mem[36];

assign d37_out = mem[37];

assign d38_out = mem[38];

assign d39_out = mem[39];

assign d40_out = mem[40];

assign d41_out = mem[41];

assign d42_out = mem[42];

assign d43_out = mem[43];

assign d44_out = mem[44];

assign d45_out = mem[45];

assign d46_out = mem[46];

assign d47_out = mem[47];

assign d48_out = mem[48];

assign d49_out = mem[49];

always @(posedge we) begin

if (i==50) i=0;

mem = Data_In[7:4];

i=i+1;

Mem[i] = Data_In[3:0];

i=i+1;

end

endmodule

Thanks,

Eran