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Altera_Forum
Honored Contributor
9 years agoI have set MSEL[4:0] to 10010, which is AS(x1 and x4) fast mode.
I also tried a pure FPGA logic controlling LED, and generated .jic files using ASx1 and ASx4 mode. Both of these two .jic files can work correctly. So the data path between FPGA and the N25Q256 should be fine.