question about Altera Cyclone 2

Cyclone II should be able to comfortably run a relatively simple counter, such as yours, at 100MHz. My concern would be what your 'trigger' looks like.

If you'd posted code with the word 'clock' instead of trigger I wouldn't have questioned it any further. You've written a reasonably sensible block of synchronous logic. Providing your 'trigger' signal looks much like a regular clock, the FPGA won't have a problem. However, if your trigger's mark/space ration is something unusual, but still generating around 100M rising edges per second, you may find iratic behaviour. Anything like this would result in the need to constrain it to operate at a higher trigger (clock) frequency.

Cheers,

Alex