Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

QuartusII Prime Pro 16.1/17.1 EMIF(DDR4) Pin Constrain Problem

Hi all, I'm trying to use Quartus II 16.1/17.1 Prime Pro with EMIF to control DDR4. The configuration is descirbed below: FPGA: 10AX066N1F40 DDR4 Config: Single-Rank, x64, Scheme 2 Number of E...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Alex,

Your understanding is correct. Ideally we want to place RZQ pin in address IOBANK which is middle of 3 IOBANK so that the signal routing can be spread balance throughout 3 IOBANK.

I am not sure what's wrong with your design but you can try place RZQ_A in pin 26 of Bank 3C or 3E and RZQ_B in pin 26 of Bank 3F,3H.

Thanks.

Regards,

spdl2001

(This message was posted on behalf of Intel Corporation)