Just another 2 cents from rbugalho's comments:
1) Yes, avoid logic muxes at all costs. The biggest problem is that there is a long delay to the muxed clock, so there is large skew from the non-muxed clock to the muxed clock. This makes timing closure between these domains difficult.
2) Sometimes you can't avoid these muxes, and you may have that issue. I've seen cases where the base clocks never feed logic, they just go through the mux. In those cases, it tends to work out pretty good. One case was multiple clocks recovered from transceivers, where one was a redundant link, and hence it could be the clock driver for all internal logic.
3) Finally, I work a lot with TQ and it's timing models, and am very impressed with all that is being modeled. So if you do muxes, and can close timing, then you should feel confident in the results. The reason these muxes should be avoided in general is they often make it harder to close timing. But it's a strong suggestion, not a rule.