--- Quote Start ---
Hi,
I have some clock muxes in the design and am using Stratix-IV GT. The Fitter automatically places the input clocks and output clocks of that clock mux in different clock tree. Thus resulting in large clock skew between the input and the output clocks.
I wish to constrain the output clock, but I am not able to get the proper object ID for that. I have tried "get_nets", "get_cells" and "get_nodes", to get the object ID of the clock mux module output port. But the "set_clock_groups" is giving warnings as these selcted objects are not of type {clk}.
Please suggest a work-around.
Thanks
Manish
--- Quote End ---
Hi,
have look into this document:
http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=cookbook Kind regards
GPK